1. Field of the Invention
The present invention relates to a memory device. More particularly, the present invention relates to a memory device utilizing vertical nanotubes.
2. Description of the Related Art
Semiconductor nonvolatile memory devices are basically comprised of a transistor, which serves as a switch for securing a current path, and a floating gate, which preserves electric charges between gates. To provide a high current flow in a transistor, the transistor must have a high transconductance property. Accordingly, there is a recent trend to use a metal-oxide-semiconductor field effect transistor (MOSFET) with a high transconductance property as a switch in a semiconductor memory device. MOSFETs are basically comprised of a control gate, formed of doped polycrystalline silicon, and a source region and a drain region, which are formed of doped crystalline silicon.
Under a certain voltage condition, the transconductance of a MOSFET is inversely proportional to a length of a channel and a thickness of a gate oxide film and directly proportional to a surface mobility, a permittivity of the gate oxide film, and a width of the channel. Since the surface mobility and the permittivity of the gate oxide film are predetermined by the materials used, i.e., silicon for a wafer, silicon oxide for the gate oxide film, etc., a high transconductance can only be secured by increasing a ratio of the width to the length of the channel or by decreasing the thickness of the gate oxide film.
To manufacture highly integrated memory devices, the size of a MOSFET must be reduced by downsizing the control gate, the source region, and the drain region. This downsizing creates several problems. For example, a reduction in the size of the control gate causes a reduction in the cross-sectional area of the control gate, such that a large electrical resistance may occur in the MOSFET. A reduction in the size of the source and drain regions causes a reduction in the thicknesses of the regions, i.e., in their junction depths, and accordingly causes a larger electrical resistance. In addition, a reduction in the distance between the source and drain regions causes a punch-through to occur where a depletion layer in the source region contacts a depletion layer in the drain regions, thereby making it impossible to control current. Such a reduction in the size of the memory device reduces the width of a channel to 30 nm or less and accordingly disrupts a smooth flow of current thereby causing the memory device to malfunction. Since conventional memory devices having silicon MOSFETs have the above-described problems when integration density increases, there is a limit in achieving highly integrated memory devices.